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<h1>/home/mandrake/rpm/BUILD/sc68-2.2.1/emu68/macro68.h File Reference</h1>68K instruction emulation macro definitions.
<a href="#_details">More...</a>
<p>
<code>#include "<a class="el" href="srdef68_8h_source.html">emu68/srdef68.h</a>"</code><br>
<code>#include "<a class="el" href="excep68_8h_source.html">emu68/excep68.h</a>"</code><br>
<p>
<a href="macro68_8h_source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6854f97787c2c6fc81de10084518e83b"></a><!-- doxytag: member="macro68.h::ADDCYCLE" ref="6854f97787c2c6fc81de10084518e83b" args="(N)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b">ADDCYCLE</a>(N)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Dummy internal cycle counter. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7f28a46e4d01a2a3aceaa1439909a969"></a><!-- doxytag: member="macro68.h::SETCYCLE" ref="7f28a46e4d01a2a3aceaa1439909a969" args="(N)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7f28a46e4d01a2a3aceaa1439909a969">SETCYCLE</a>(N)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Dummy internal cycle counter. <br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Exception handling.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#20a4f9d1130f259f69dab9c2b32a78e1">EXCEPTION</a>(VECTOR, LVL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">General exception or interruption. <a href="#20a4f9d1130f259f69dab9c2b32a78e1"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#50f4496a33308c2325e5c9cea9ccd9f2">ILLEGAL</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Illegal instruction. <a href="#50f4496a33308c2325e5c9cea9ccd9f2"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#be98308cc3e5190044294f4f626b4442">BUSERROR</a>(ADDR, MODE)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Bus error exception. <a href="#be98308cc3e5190044294f4f626b4442"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ecf2e1f677876da4397423d9d2bd08e2"></a><!-- doxytag: member="macro68.h::LINEA" ref="ecf2e1f677876da4397423d9d2bd08e2" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#ecf2e1f677876da4397423d9d2bd08e2">LINEA</a> EXCEPTION(LINEA_VECTOR,LINEA_LVL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Line A exception. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f237af18c5657f78a1bb0c8434b5cc8d"></a><!-- doxytag: member="macro68.h::LINEF" ref="f237af18c5657f78a1bb0c8434b5cc8d" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#f237af18c5657f78a1bb0c8434b5cc8d">LINEF</a> EXCEPTION(LINEF_VECTOR,LINEF_LVL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Line F exception. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="28d5b3accc8e77e4dbb4da615d46312f"></a><!-- doxytag: member="macro68.h::TRAPV" ref="28d5b3accc8e77e4dbb4da615d46312f" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#28d5b3accc8e77e4dbb4da615d46312f">TRAPV</a> if(reg68.sr&SR_V) EXCEPTION(TRAPV_VECTOR,TRAPV_LVL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">TRAPV exception. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b677c17b45660f2cbea68ef8784d017f"></a><!-- doxytag: member="macro68.h::TRAP" ref="b677c17b45660f2cbea68ef8784d017f" args="(TRAP_N)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#b677c17b45660f2cbea68ef8784d017f">TRAP</a>(TRAP_N) EXCEPTION(TRAP_VECTOR(TRAP_N),TRAP_LVL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">TRAP exception. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5ccabf1aaaf2408ff4bec6b4a27d076b"></a><!-- doxytag: member="macro68.h::CHK" ref="5ccabf1aaaf2408ff4bec6b4a27d076b" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#5ccabf1aaaf2408ff4bec6b4a27d076b">CHK</a> EXCEPTION(CHK_VECTOR,CHK_LVL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">CHK exception. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7fef6081b06bc5ee2638625313745c4e"></a><!-- doxytag: member="macro68.h::CHKW" ref="7fef6081b06bc5ee2638625313745c4e" args="(CHK_A, CHK_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7fef6081b06bc5ee2638625313745c4e">CHKW</a>(CHK_A, CHK_B) if((CHK_B)<0 || (CHK_B)>(CHK_A)){ CHK; }</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">CHKW exception. <br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Program control instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="700f88377bf36711b711f69b06c52f5d"></a><!-- doxytag: member="macro68.h::NOP" ref="700f88377bf36711b711f69b06c52f5d" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#700f88377bf36711b711f69b06c52f5d">NOP</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">No Operation. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b702106cf3b3e96750b6845ded4e0299"></a><!-- doxytag: member="macro68.h::RESET" ref="b702106cf3b3e96750b6845ded4e0299" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#b702106cf3b3e96750b6845ded4e0299">RESET</a> EMU68_reset()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Soft reset. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#e19b6bb2940d2fbe0a79852b070eeafd">STOP</a> reg68.sr = (<a class="el" href="type68_8h.html#9e6c91d77e24643b888dbd1a1a590054">u16</a>)get_nextw(); reg68.status = 1</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">STOP. <a href="#e19b6bb2940d2fbe0a79852b070eeafd"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5da46cdb9a2133d1b4f0db71a332ba2e"></a><!-- doxytag: member="macro68.h::RTS" ref="5da46cdb9a2133d1b4f0db71a332ba2e" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#5da46cdb9a2133d1b4f0db71a332ba2e">RTS</a> reg68.pc = popl()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return from subroutine. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5807d8becfd6e182041e4ccca3eeb20a"></a><!-- doxytag: member="macro68.h::RTE" ref="5807d8becfd6e182041e4ccca3eeb20a" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#5807d8becfd6e182041e4ccca3eeb20a">RTE</a> reg68.sr = popw(); RTS</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return from exception. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8f14d04b8bcaf04226f4fe5c112b60aa"></a><!-- doxytag: member="macro68.h::RTR" ref="8f14d04b8bcaf04226f4fe5c112b60aa" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#8f14d04b8bcaf04226f4fe5c112b60aa">RTR</a> reg68.sr = (reg68.sr&0xFF00) | (u8)popw(); RTS</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return from exception restore CCR only. <br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Miscellaneous instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e57f476554857ff7dbf3925a1854c1be"></a><!-- doxytag: member="macro68.h::NBCDB" ref="e57f476554857ff7dbf3925a1854c1be" args="(NBCD_S, NBCD_A)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#e57f476554857ff7dbf3925a1854c1be">NBCDB</a>(NBCD_S, NBCD_A) (NBCD_S)=(NBCD_A)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Binary coded decimal sign change. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2028670c42d483d106c2f088c9ae7e1a"></a><!-- doxytag: member="macro68.h::EXG" ref="2028670c42d483d106c2f088c9ae7e1a" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#2028670c42d483d106c2f088c9ae7e1a">EXG</a>(A, B) (A)^=(B); (B)^=(A); (A)^=(B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Register MSW/LSW exchange. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="43ba1e48ab3e4ae9e15e9b2894bd9fbe"></a><!-- doxytag: member="macro68.h::EXTW" ref="43ba1e48ab3e4ae9e15e9b2894bd9fbe" args="(D)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#43ba1e48ab3e4ae9e15e9b2894bd9fbe">EXTW</a>(D) (D) = ((D)&0xFFFF0000) | ((u16)(s32)(s8)(D))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte to word sign extension. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4a60eb72a9bde7ad33449dcd956d8872"></a><!-- doxytag: member="macro68.h::EXTL" ref="4a60eb72a9bde7ad33449dcd956d8872" args="(D)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#4a60eb72a9bde7ad33449dcd956d8872">EXTL</a>(D) (D) = (<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a>)(<a class="el" href="type68_8h.html#5ffa4f640862b25ba6d4f635b78bdbe1">s16</a>)(D)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word to long sign extension. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1dcb91751f0ea83de1926fe31edc308b"></a><!-- doxytag: member="macro68.h::TAS" ref="1dcb91751f0ea83de1926fe31edc308b" args="(TAS_A)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#1dcb91751f0ea83de1926fe31edc308b">TAS</a>(TAS_A) { TSTB(TAS_A,TAS_A); (TAS_A) |= 0x80000000; }</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Test and set (mutual exclusion). <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#0cbf0b9c373ada722f2e3940a8e837a3">CLR</a>(CLR_S, CLR_A)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic clear memory or register. <a href="#0cbf0b9c373ada722f2e3940a8e837a3"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3999d24bd7bc6cd9fe716fe66a0309f3"></a><!-- doxytag: member="macro68.h::CLRB" ref="3999d24bd7bc6cd9fe716fe66a0309f3" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#3999d24bd7bc6cd9fe716fe66a0309f3">CLRB</a>(A, B) CLR(A,B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte memory or register clear. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8131676f4c04dc5ed97cb90f905d1db9"></a><!-- doxytag: member="macro68.h::CLRW" ref="8131676f4c04dc5ed97cb90f905d1db9" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#8131676f4c04dc5ed97cb90f905d1db9">CLRW</a>(A, B) CLR(A,B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word memory or register clear. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6a54e13ddc6874c7163c95c71cb661a4"></a><!-- doxytag: member="macro68.h::CLRL" ref="6a54e13ddc6874c7163c95c71cb661a4" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#6a54e13ddc6874c7163c95c71cb661a4">CLRL</a>(A, B) CLR(A,B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long memory or register clear. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#cabdc746fdfa7e8a587104efcd13b145">LINK</a>(R_LNK)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Link (frame pointer). <a href="#cabdc746fdfa7e8a587104efcd13b145"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#207482409eaa458a93dc02f7f89a55fe">UNLK</a>(R_LNK)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">UNLK (frame pointer). <a href="#207482409eaa458a93dc02f7f89a55fe"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#437700508dff5a665d62caed6d19962a">SWAP</a>(SWP_A)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Register value swapping. <a href="#437700508dff5a665d62caed6d19962a"></a><br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bit instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cbec8f78bfb513f8ef386bc0cb37140d"></a><!-- doxytag: member="macro68.h::BTST" ref="cbec8f78bfb513f8ef386bc0cb37140d" args="(V, BIT)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#cbec8f78bfb513f8ef386bc0cb37140d">BTST</a>(V, BIT) reg68.sr = (reg68.sr&(~SR_Z)) | (((((V)>>(BIT))&1)^1)<<SR_Z_BIT)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Bit test and set. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#9e3dfa1ebebfd77f10b81218e221b141">BSET</a>(V, BIT)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Bit set. <a href="#9e3dfa1ebebfd77f10b81218e221b141"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#9c1e975d7c0e874a2110b6bb1c26fe1a">BCLR</a>(V, BIT)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Bit clear. <a href="#9c1e975d7c0e874a2110b6bb1c26fe1a"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#09f70aac938aa9c8b83269d32d347121">BCHG</a>(V, BIT)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Bit change. <a href="#09f70aac938aa9c8b83269d32d347121"></a><br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Move & test instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><b>MOVE</b>(MOV_A)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b6100b809e581700b4b0c985455ed2ab"></a><!-- doxytag: member="macro68.h::TST" ref="b6100b809e581700b4b0c985455ed2ab" args="(TST_V)" -->
#define </td><td class="memItemRight" valign="bottom"><b>TST</b>(TST_V) MOVE(TST_V)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="970ed42a7a736265772d327037a590aa"></a><!-- doxytag: member="macro68.h::TSTB" ref="970ed42a7a736265772d327037a590aa" args="(TST_S, TST_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>TSTB</b>(TST_S, TST_A) { TST_S=TST_A; TST(TST_S); }</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5dfbbde8693d9c83d8fab2cca7436fe9"></a><!-- doxytag: member="macro68.h::TSTW" ref="5dfbbde8693d9c83d8fab2cca7436fe9" args="(TST_S, TST_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>TSTW</b>(TST_S, TST_A) { TST_S=TST_A; TST(TST_S); }</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="420568b7be5592caecc4714cc2990aea"></a><!-- doxytag: member="macro68.h::TSTL" ref="420568b7be5592caecc4714cc2990aea" args="(TST_S, TST_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>TSTL</b>(TST_S, TST_A) { TST_S=TST_A; TST(TST_S); }</td></tr>
<tr><td colspan="2"><div class="groupHeader">Multiply & Divide instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dad07bc9c659173706c0e00bfdd2824c"></a><!-- doxytag: member="macro68.h::MULSW" ref="dad07bc9c659173706c0e00bfdd2824c" args="(MUL_S, MUL_A, MUL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#dad07bc9c659173706c0e00bfdd2824c">MULSW</a>(MUL_S, MUL_A, MUL_B) MUL_S = muls68(MUL_A, MUL_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Signed multiplication. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="26c07b161cd6aa0439daf3d933a92697"></a><!-- doxytag: member="macro68.h::MULUW" ref="26c07b161cd6aa0439daf3d933a92697" args="(MUL_S, MUL_A, MUL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#26c07b161cd6aa0439daf3d933a92697">MULUW</a>(MUL_S, MUL_A, MUL_B) MUL_S = mulu68(MUL_A, MUL_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Unsigned multiplication. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ad5f7e9d536c30813ccef8826b5fcb71"></a><!-- doxytag: member="macro68.h::DIVSW" ref="ad5f7e9d536c30813ccef8826b5fcb71" args="(DIV_S, DIV_A, DIV_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#ad5f7e9d536c30813ccef8826b5fcb71">DIVSW</a>(DIV_S, DIV_A, DIV_B) DIV_S = divs68(DIV_A, DIV_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Signed divide. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2f4b35c99a2948f04c62c714e682bf2"></a><!-- doxytag: member="macro68.h::DIVUW" ref="c2f4b35c99a2948f04c62c714e682bf2" args="(DIV_S, DIV_A, DIV_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#c2f4b35c99a2948f04c62c714e682bf2">DIVUW</a>(DIV_S, DIV_A, DIV_B) DIV_S = divu68(DIV_A, DIV_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Unsigned divide. <br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Logical instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="728e137c866ee949f69816a2ceff539a"></a><!-- doxytag: member="macro68.h::AND" ref="728e137c866ee949f69816a2ceff539a" args="(AND_S, AND_A, AND_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#728e137c866ee949f69816a2ceff539a">AND</a>(AND_S, AND_A, AND_B) AND_S = and68(AND_A, AND_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic bitwise AND. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d972449d7e05ae60764f4eb2620e025e"></a><!-- doxytag: member="macro68.h::ANDB" ref="d972449d7e05ae60764f4eb2620e025e" args="(AND_S, AND_A, AND_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#d972449d7e05ae60764f4eb2620e025e">ANDB</a>(AND_S, AND_A, AND_B) AND(AND_S, AND_A, AND_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte bitwise AND. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d63151cdbcf39fd2fa6b240bb0bb3f0"></a><!-- doxytag: member="macro68.h::ANDW" ref="8d63151cdbcf39fd2fa6b240bb0bb3f0" args="(AND_S, AND_A, AND_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#8d63151cdbcf39fd2fa6b240bb0bb3f0">ANDW</a>(AND_S, AND_A, AND_B) AND(AND_S, AND_A, AND_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word bitwise AND. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="79954b6e88c6b20e566ab890fe051d9a"></a><!-- doxytag: member="macro68.h::ANDL" ref="79954b6e88c6b20e566ab890fe051d9a" args="(AND_S, AND_A, AND_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#79954b6e88c6b20e566ab890fe051d9a">ANDL</a>(AND_S, AND_A, AND_B) AND(AND_S, AND_A, AND_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long bitwise AND. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="677d883d40a07fb971e3496cc99701c0"></a><!-- doxytag: member="macro68.h::ORR" ref="677d883d40a07fb971e3496cc99701c0" args="(ORR_S, ORR_A, ORR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#677d883d40a07fb971e3496cc99701c0">ORR</a>(ORR_S, ORR_A, ORR_B) ORR_S = orr68(ORR_A, ORR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic bitwise OR. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c4a543252cc9b0f8f418a74444d66fa4"></a><!-- doxytag: member="macro68.h::ORB" ref="c4a543252cc9b0f8f418a74444d66fa4" args="(ORR_S, ORR_A, ORR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#c4a543252cc9b0f8f418a74444d66fa4">ORB</a>(ORR_S, ORR_A, ORR_B) ORR(ORR_S, ORR_A, ORR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte bitwise OR. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c9ac7a69fad700b345e43e5481f41e31"></a><!-- doxytag: member="macro68.h::ORW" ref="c9ac7a69fad700b345e43e5481f41e31" args="(ORR_S, ORR_A, ORR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#c9ac7a69fad700b345e43e5481f41e31">ORW</a>(ORR_S, ORR_A, ORR_B) ORR(ORR_S, ORR_A, ORR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word bitwise OR. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d287e8a16c1f3d00e0b4e5b19ee996c8"></a><!-- doxytag: member="macro68.h::ORL" ref="d287e8a16c1f3d00e0b4e5b19ee996c8" args="(ORR_S, ORR_A, ORR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#d287e8a16c1f3d00e0b4e5b19ee996c8">ORL</a>(ORR_S, ORR_A, ORR_B) ORR(ORR_S, ORR_A, ORR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long bitwise OR. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="44b282cbcfb2007767762a301c7a00ae"></a><!-- doxytag: member="macro68.h::EOR" ref="44b282cbcfb2007767762a301c7a00ae" args="(EOR_S, EOR_A, EOR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#44b282cbcfb2007767762a301c7a00ae">EOR</a>(EOR_S, EOR_A, EOR_B) EOR_S = eor68(EOR_A, EOR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic bitwise EOR (exclusive OR). <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3708773ba26e7cb77a64dc8dfa2ae4c1"></a><!-- doxytag: member="macro68.h::EORB" ref="3708773ba26e7cb77a64dc8dfa2ae4c1" args="(EOR_S, EOR_A, EOR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#3708773ba26e7cb77a64dc8dfa2ae4c1">EORB</a>(EOR_S, EOR_A, EOR_B) EOR(EOR_S, EOR_A, EOR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte bitwise EOR (exclusif OR). <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ea4de1f4ef50628e47a816a2c365cdbd"></a><!-- doxytag: member="macro68.h::EORW" ref="ea4de1f4ef50628e47a816a2c365cdbd" args="(EOR_S, EOR_A, EOR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#ea4de1f4ef50628e47a816a2c365cdbd">EORW</a>(EOR_S, EOR_A, EOR_B) EOR(EOR_S, EOR_A, EOR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word bitwise EOR (exclusif OR). <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="44bbd20b80c6bdb4d15d6029d615ac2b"></a><!-- doxytag: member="macro68.h::EORL" ref="44bbd20b80c6bdb4d15d6029d615ac2b" args="(EOR_S, EOR_A, EOR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#44bbd20b80c6bdb4d15d6029d615ac2b">EORL</a>(EOR_S, EOR_A, EOR_B) EOR(EOR_S, EOR_A, EOR_B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long bitwise EOR (exclusif OR). <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1eae181b74b282ebd1d358b903520433"></a><!-- doxytag: member="macro68.h::NOT" ref="1eae181b74b282ebd1d358b903520433" args="(NOT_S, NOT_A)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#1eae181b74b282ebd1d358b903520433">NOT</a>(NOT_S, NOT_A) NOT_S = not68(NOT_A)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic first complement. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e2b11e2a5a2c48dd9ead9519b12f9f1"></a><!-- doxytag: member="macro68.h::NOTB" ref="3e2b11e2a5a2c48dd9ead9519b12f9f1" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#3e2b11e2a5a2c48dd9ead9519b12f9f1">NOTB</a>(A, B) NOT(A,B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte first complement. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7003129e40217ac4bcf15d3a8aeab0e5"></a><!-- doxytag: member="macro68.h::NOTW" ref="7003129e40217ac4bcf15d3a8aeab0e5" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7003129e40217ac4bcf15d3a8aeab0e5">NOTW</a>(A, B) NOT(A,B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word first complement. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1afffa6abcc68afc2f0411089572e795"></a><!-- doxytag: member="macro68.h::NOTL" ref="1afffa6abcc68afc2f0411089572e795" args="(A, B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#1afffa6abcc68afc2f0411089572e795">NOTL</a>(A, B) NOT(A,B)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long first complement. <br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Arithmetic instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3df193fd54249ec0ca0e4ed0aa961629"></a><!-- doxytag: member="macro68.h::ADD" ref="3df193fd54249ec0ca0e4ed0aa961629" args="(ADD_S, ADD_A, ADD_B, ADD_X)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADD</b>(ADD_S, ADD_A, ADD_B, ADD_X) ADD_S=add68(ADD_A,ADD_B,ADD_X)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="875bfa167b81cb4dd7a565d063e67ef7"></a><!-- doxytag: member="macro68.h::SUB" ref="875bfa167b81cb4dd7a565d063e67ef7" args="(SUB_S, SUB_A, SUB_B, SUB_X)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUB</b>(SUB_S, SUB_A, SUB_B, SUB_X) SUB_S=sub68(SUB_B,SUB_A,SUB_X)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="42ee565ba811ce7c804570eff5442cbb"></a><!-- doxytag: member="macro68.h::CMP" ref="42ee565ba811ce7c804570eff5442cbb" args="(SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>CMP</b>(SUB_A, SUB_B) sub68(SUB_B,SUB_A,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d3e10c0d8e9620d47a0d0924f81ed947"></a><!-- doxytag: member="macro68.h::ADDB" ref="d3e10c0d8e9620d47a0d0924f81ed947" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDB</b>(ADD_S, ADD_A, ADD_B) ADD(ADD_S, ADD_A, ADD_B,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="36e1fb54dd8acbad27547d1d25ec1660"></a><!-- doxytag: member="macro68.h::ADDW" ref="36e1fb54dd8acbad27547d1d25ec1660" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDW</b>(ADD_S, ADD_A, ADD_B) ADD(ADD_S, ADD_A, ADD_B,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ab21e2bf8f411b6b669ebba9511889ee"></a><!-- doxytag: member="macro68.h::ADDL" ref="ab21e2bf8f411b6b669ebba9511889ee" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDL</b>(ADD_S, ADD_A, ADD_B) ADD(ADD_S, ADD_A, ADD_B,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3ef284fce14f13f812f85c6d2902e74a"></a><!-- doxytag: member="macro68.h::ADDXB" ref="3ef284fce14f13f812f85c6d2902e74a" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDXB</b>(ADD_S, ADD_A, ADD_B) ADD(ADD_S, ADD_A, ADD_B, (reg68.sr&SR_X)<<(24-SR_X_BIT))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="566d977d66bbefa6dd1fafad418b7a5a"></a><!-- doxytag: member="macro68.h::ADDXW" ref="566d977d66bbefa6dd1fafad418b7a5a" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDXW</b>(ADD_S, ADD_A, ADD_B) ADD(ADD_S, ADD_A, ADD_B, (reg68.sr&SR_X)<<(16-SR_X_BIT))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07ba6325a2919003e28a9a27d060e0bc"></a><!-- doxytag: member="macro68.h::ADDXL" ref="07ba6325a2919003e28a9a27d060e0bc" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDXL</b>(ADD_S, ADD_A, ADD_B) ADD(ADD_S, ADD_A, ADD_B, (reg68.sr&SR_X)>>SR_X_BIT )</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="425f98fefd195e2ab2b80b433a76d5a8"></a><!-- doxytag: member="macro68.h::ADDA" ref="425f98fefd195e2ab2b80b433a76d5a8" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDA</b>(ADD_S, ADD_A, ADD_B) (ADD_S) = (ADD_A) + (ADD_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="74163efeb79c0fa3cb39288dd2deb6b3"></a><!-- doxytag: member="macro68.h::ADDAW" ref="74163efeb79c0fa3cb39288dd2deb6b3" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDAW</b>(ADD_S, ADD_A, ADD_B) ADDA(ADD_S, ADD_A>>16, ADD_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="69aa6ca21585c2ad4df8168f82a77c26"></a><!-- doxytag: member="macro68.h::ADDAL" ref="69aa6ca21585c2ad4df8168f82a77c26" args="(ADD_S, ADD_A, ADD_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>ADDAL</b>(ADD_S, ADD_A, ADD_B) ADDA(ADD_S, ADD_A, ADD_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3f025f9710aa6d5b385c0cfed34a07d2"></a><!-- doxytag: member="macro68.h::SUBB" ref="3f025f9710aa6d5b385c0cfed34a07d2" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBB</b>(SUB_S, SUB_A, SUB_B) SUB(SUB_S, SUB_A, SUB_B,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="40c5bdd0e35bf77e18cdf5f5e8e35263"></a><!-- doxytag: member="macro68.h::SUBW" ref="40c5bdd0e35bf77e18cdf5f5e8e35263" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBW</b>(SUB_S, SUB_A, SUB_B) SUB(SUB_S, SUB_A, SUB_B,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b7b0b91cdfc1bae1741fa785dae7152b"></a><!-- doxytag: member="macro68.h::SUBL" ref="b7b0b91cdfc1bae1741fa785dae7152b" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBL</b>(SUB_S, SUB_A, SUB_B) SUB(SUB_S, SUB_A, SUB_B,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="00ac1f3c194a6a769aa5b51bcba5c462"></a><!-- doxytag: member="macro68.h::SUBXB" ref="00ac1f3c194a6a769aa5b51bcba5c462" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBXB</b>(SUB_S, SUB_A, SUB_B) SUB(SUB_S, SUB_A, SUB_B, (reg68.sr&SR_X)<<(24-SR_X_BIT))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0839621a70e4cf5360bf1efa76cd6317"></a><!-- doxytag: member="macro68.h::SUBXW" ref="0839621a70e4cf5360bf1efa76cd6317" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBXW</b>(SUB_S, SUB_A, SUB_B) SUB(SUB_S, SUB_A, SUB_B, (reg68.sr&SR_X)<<(16-SR_X_BIT))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="48e21297874954c3d85789334a441c96"></a><!-- doxytag: member="macro68.h::SUBXL" ref="48e21297874954c3d85789334a441c96" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBXL</b>(SUB_S, SUB_A, SUB_B) SUB(SUB_S, SUB_A, SUB_B, (reg68.sr&SR_X)>>SR_X_BIT)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="23303fc54fabbce445e8764af26b5bfd"></a><!-- doxytag: member="macro68.h::SUBA" ref="23303fc54fabbce445e8764af26b5bfd" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBA</b>(SUB_S, SUB_A, SUB_B) (SUB_S) = (SUB_B) - (SUB_A)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><b>SUBAW</b>(SUB_S, SUB_A, SUB_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b50bd545c3a957f8950634c20b2093d3"></a><!-- doxytag: member="macro68.h::SUBAL" ref="b50bd545c3a957f8950634c20b2093d3" args="(SUB_S, SUB_A, SUB_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>SUBAL</b>(SUB_S, SUB_A, SUB_B) SUBA(SUB_S, SUB_A, SUB_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b4cd40ecd82220fa254daa475f8394ff"></a><!-- doxytag: member="macro68.h::CMPB" ref="b4cd40ecd82220fa254daa475f8394ff" args="(CMP_A, CMP_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>CMPB</b>(CMP_A, CMP_B) CMP(CMP_A, CMP_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3bec17b5a9001975fd940fb5ecea4e4d"></a><!-- doxytag: member="macro68.h::CMPW" ref="3bec17b5a9001975fd940fb5ecea4e4d" args="(CMP_A, CMP_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>CMPW</b>(CMP_A, CMP_B) CMP(CMP_A, CMP_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="64b2f9277ea3ced03bd1b67b52a06145"></a><!-- doxytag: member="macro68.h::CMPL" ref="64b2f9277ea3ced03bd1b67b52a06145" args="(CMP_A, CMP_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>CMPL</b>(CMP_A, CMP_B) CMP(CMP_A, CMP_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b3507cfed2088333a68d91c4d789bcfe"></a><!-- doxytag: member="macro68.h::CMPA" ref="b3507cfed2088333a68d91c4d789bcfe" args="(CMP_A, CMP_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>CMPA</b>(CMP_A, CMP_B) CMP(CMP_A, CMP_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><b>CMPAW</b>(CMP_A, CMP_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ba63364c6486019f23d8ac9ba210b902"></a><!-- doxytag: member="macro68.h::CMPAL" ref="ba63364c6486019f23d8ac9ba210b902" args="(CMP_A, CMP_B)" -->
#define </td><td class="memItemRight" valign="bottom"><b>CMPAL</b>(CMP_A, CMP_B) CMP(CMP_A, CMP_B)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4890b8fa730808e5f748575add55e745"></a><!-- doxytag: member="macro68.h::NEGB" ref="4890b8fa730808e5f748575add55e745" args="(NEG_S, NEG_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>NEGB</b>(NEG_S, NEG_A) SUBB(NEG_S,NEG_A,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ed47fc2d27ebeaefdb97c60b51a5ca0"></a><!-- doxytag: member="macro68.h::NEGW" ref="7ed47fc2d27ebeaefdb97c60b51a5ca0" args="(NEG_S, NEG_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>NEGW</b>(NEG_S, NEG_A) SUBW(NEG_S,NEG_A,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2600182eaa13afd5118369b870298b61"></a><!-- doxytag: member="macro68.h::NEGL" ref="2600182eaa13afd5118369b870298b61" args="(NEG_S, NEG_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>NEGL</b>(NEG_S, NEG_A) SUBL(NEG_S,NEG_A,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bfdae93cbb6129d6276a5b9ca381e2fb"></a><!-- doxytag: member="macro68.h::NEGXB" ref="bfdae93cbb6129d6276a5b9ca381e2fb" args="(NEG_S, NEG_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>NEGXB</b>(NEG_S, NEG_A) SUBXB(NEG_S,NEG_A,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f29709278ef64b4d23db84972313b1ea"></a><!-- doxytag: member="macro68.h::NEGXW" ref="f29709278ef64b4d23db84972313b1ea" args="(NEG_S, NEG_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>NEGXW</b>(NEG_S, NEG_A) SUBXW(NEG_S,NEG_A,0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ee55bf295459d52e4a9a8addca312e65"></a><!-- doxytag: member="macro68.h::NEGXL" ref="ee55bf295459d52e4a9a8addca312e65" args="(NEG_S, NEG_A)" -->
#define </td><td class="memItemRight" valign="bottom"><b>NEGXL</b>(NEG_S, NEG_A) SUBXL(NEG_S,NEG_A,0)</td></tr>
<tr><td colspan="2"><div class="groupHeader">Logical & Arithmetic bit shifting instructions.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#62f78dccd3f300863730f230b762b17b">LSR</a>(LSR_A, LSR_D, LSR_MSK, LSR_C)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <a href="#62f78dccd3f300863730f230b762b17b"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="66eee939032d569aae1c9e2af2a153ae"></a><!-- doxytag: member="macro68.h::LSRB" ref="66eee939032d569aae1c9e2af2a153ae" args="(LSR_A, LSR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#66eee939032d569aae1c9e2af2a153ae">LSRB</a>(LSR_A, LSR_B) LSR(LSR_A,LSR_B,0xFF000000,(1<<24))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte logical right shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cda251ffd0e1c91d6719b77c58ef53a7"></a><!-- doxytag: member="macro68.h::LSRW" ref="cda251ffd0e1c91d6719b77c58ef53a7" args="(LSR_A, LSR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#cda251ffd0e1c91d6719b77c58ef53a7">LSRW</a>(LSR_A, LSR_B) LSR(LSR_A,LSR_B,0xFFFF0000,(1<<16))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word logical right shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="389f0f970a4b922262fca9142e81f5b8"></a><!-- doxytag: member="macro68.h::LSRL" ref="389f0f970a4b922262fca9142e81f5b8" args="(LSR_A, LSR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#389f0f970a4b922262fca9142e81f5b8">LSRL</a>(LSR_A, LSR_B) LSR(LSR_A,LSR_B,0xFFFFFFFF,(1<<0))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long logical right shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fda032ebebb1ac2422b6294d946ffd57"></a><!-- doxytag: member="macro68.h::ASRB" ref="fda032ebebb1ac2422b6294d946ffd57" args="(LSR_A, LSR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#fda032ebebb1ac2422b6294d946ffd57">ASRB</a>(LSR_A, LSR_B) LSR(LSR_A,LSR_B,0xFF000000,(1<<24))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte arithmetic right shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="352408838f3c61c43436d81b5ccf4f55"></a><!-- doxytag: member="macro68.h::ASRW" ref="352408838f3c61c43436d81b5ccf4f55" args="(LSR_A, LSR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#352408838f3c61c43436d81b5ccf4f55">ASRW</a>(LSR_A, LSR_B) LSR(LSR_A,LSR_B,0xFFFF0000,(1<<16))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word arithmetic right shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1de7c77e7fdc80cf4d18e60b5d9de4ff"></a><!-- doxytag: member="macro68.h::ASRL" ref="1de7c77e7fdc80cf4d18e60b5d9de4ff" args="(LSR_A, LSR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#1de7c77e7fdc80cf4d18e60b5d9de4ff">ASRL</a>(LSR_A, LSR_B) LSR(LSR_A,LSR_B,0xFFFFFFFF,(1<<0))</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long arithmetic right shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#32f934a87ef94acfd506fba08a9df435">LSL</a>(LSL_A, LSL_D, LSL_MSK)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic left shift. <a href="#32f934a87ef94acfd506fba08a9df435"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="472d1ec4b53c4722473b9c0535338cb5"></a><!-- doxytag: member="macro68.h::LSLB" ref="472d1ec4b53c4722473b9c0535338cb5" args="(LSL_A, LSL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#472d1ec4b53c4722473b9c0535338cb5">LSLB</a>(LSL_A, LSL_B) LSL(LSL_A,LSL_B,0xFF000000)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte logical left shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c850ec650a19af8c36146905bebd269b"></a><!-- doxytag: member="macro68.h::LSLW" ref="c850ec650a19af8c36146905bebd269b" args="(LSL_A, LSL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#c850ec650a19af8c36146905bebd269b">LSLW</a>(LSL_A, LSL_B) LSL(LSL_A,LSL_B,0xFFFF0000)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word logical left shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="956a2dcbf6030d19cd5b71ba7827727d"></a><!-- doxytag: member="macro68.h::LSLL" ref="956a2dcbf6030d19cd5b71ba7827727d" args="(LSL_A, LSL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#956a2dcbf6030d19cd5b71ba7827727d">LSLL</a>(LSL_A, LSL_B) LSL(LSL_A,LSL_B,0xFFFFFFFF)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long logical left shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1dd79a92be184f728f8334444021fff6"></a><!-- doxytag: member="macro68.h::ASLB" ref="1dd79a92be184f728f8334444021fff6" args="(LSL_A, LSL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#1dd79a92be184f728f8334444021fff6">ASLB</a>(LSL_A, LSL_B) LSL(LSL_A,LSL_B,0xFF000000)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Byte arithmetic left shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="54ce6271abd10badaf2403522085e0e9"></a><!-- doxytag: member="macro68.h::ASLW" ref="54ce6271abd10badaf2403522085e0e9" args="(LSL_A, LSL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#54ce6271abd10badaf2403522085e0e9">ASLW</a>(LSL_A, LSL_B) LSL(LSL_A,LSL_B,0xFFFF0000)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Word arithmetic left shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02ada02c27ff61f9cc45f7387df01777"></a><!-- doxytag: member="macro68.h::ASLL" ref="02ada02c27ff61f9cc45f7387df01777" args="(LSL_A, LSL_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#02ada02c27ff61f9cc45f7387df01777">ASLL</a>(LSL_A, LSL_B) LSL(LSL_A,LSL_B,0xFFFFFFFF)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Long arithmetic left shift. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#b68fd08adcd92db17b1105faedc53039">ROR</a>(ROR_A, ROR_D, ROR_MSK, ROR_SZ)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic right rotation. <a href="#b68fd08adcd92db17b1105faedc53039"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#9256b88e92d07a399381ca524df5ee31">ROL</a>(ROR_A, ROR_D, ROR_MSK, ROR_SZ)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic left rotation. <a href="#9256b88e92d07a399381ca524df5ee31"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cfbef3b4e05471e05c4596d0aa54b384"></a><!-- doxytag: member="macro68.h::RORB" ref="cfbef3b4e05471e05c4596d0aa54b384" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#cfbef3b4e05471e05c4596d0aa54b384">RORB</a>(ROR_A, ROR_B) ROR(ROR_A,ROR_B,0xFF000000,8)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2c1f7cf90cc50e238686514c1d783be8"></a><!-- doxytag: member="macro68.h::RORW" ref="2c1f7cf90cc50e238686514c1d783be8" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#2c1f7cf90cc50e238686514c1d783be8">RORW</a>(ROR_A, ROR_B) ROR(ROR_A,ROR_B,0xFFFF0000,16)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2e740f350e0ba80253ff697d1b909565"></a><!-- doxytag: member="macro68.h::RORL" ref="2e740f350e0ba80253ff697d1b909565" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#2e740f350e0ba80253ff697d1b909565">RORL</a>(ROR_A, ROR_B) ROR(ROR_A,ROR_B,0xFFFFFFFF,32)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d4c0c47790b729de2c55e40f943ea7fb"></a><!-- doxytag: member="macro68.h::ROLB" ref="d4c0c47790b729de2c55e40f943ea7fb" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#d4c0c47790b729de2c55e40f943ea7fb">ROLB</a>(ROR_A, ROR_B) ROL(ROR_A,ROR_B,0xFF000000,8)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7a7b5d18bb3967e9d43a983ba02cd0b0"></a><!-- doxytag: member="macro68.h::ROLW" ref="7a7b5d18bb3967e9d43a983ba02cd0b0" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7a7b5d18bb3967e9d43a983ba02cd0b0">ROLW</a>(ROR_A, ROR_B) ROL(ROR_A,ROR_B,0xFFFF0000,16)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e2c9f437b5dd44922be57fa9d4d510a6"></a><!-- doxytag: member="macro68.h::ROLL" ref="e2c9f437b5dd44922be57fa9d4d510a6" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#e2c9f437b5dd44922be57fa9d4d510a6">ROLL</a>(ROR_A, ROR_B) ROL(ROR_A,ROR_B,0xFFFFFFFF,32)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#c345ba876fb038f47a015001da1552f5">ROXR</a>(ROR_A, ROR_D, ROR_MSK, ROR_SZ)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic right extend-bit rotation. <a href="#c345ba876fb038f47a015001da1552f5"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#fc5f222e265883f0ef3153798efa2cce">ROXL</a>(ROR_A, ROR_D, ROR_MSK, ROR_SZ)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic left extend-bit rotation. <a href="#fc5f222e265883f0ef3153798efa2cce"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2cd8b05d04680b28e8a2270bdebb6605"></a><!-- doxytag: member="macro68.h::ROXRB" ref="2cd8b05d04680b28e8a2270bdebb6605" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#2cd8b05d04680b28e8a2270bdebb6605">ROXRB</a>(ROR_A, ROR_B) ROXR(ROR_A,ROR_B,0xFF000000,8)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7c418e09442d42c45b6862ecee08a7dc"></a><!-- doxytag: member="macro68.h::ROXRW" ref="7c418e09442d42c45b6862ecee08a7dc" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7c418e09442d42c45b6862ecee08a7dc">ROXRW</a>(ROR_A, ROR_B) ROXR(ROR_A,ROR_B,0xFFFF0000,16)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7636eecc52eaa317970783b8ca5c5cf2"></a><!-- doxytag: member="macro68.h::ROXRL" ref="7636eecc52eaa317970783b8ca5c5cf2" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7636eecc52eaa317970783b8ca5c5cf2">ROXRL</a>(ROR_A, ROR_B) ROXR(ROR_A,ROR_B,0xFFFFFFFF,32)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7bcc76eb72635990f7d4bee3ce228527"></a><!-- doxytag: member="macro68.h::ROXLB" ref="7bcc76eb72635990f7d4bee3ce228527" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#7bcc76eb72635990f7d4bee3ce228527">ROXLB</a>(ROR_A, ROR_B) ROXL(ROR_A,ROR_B,0xFF000000,8)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f1d291e1d8ddf7df1429b9e96a79a003"></a><!-- doxytag: member="macro68.h::ROXLW" ref="f1d291e1d8ddf7df1429b9e96a79a003" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#f1d291e1d8ddf7df1429b9e96a79a003">ROXLW</a>(ROR_A, ROR_B) ROXL(ROR_A,ROR_B,0xFFFF0000,16)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8ea628cee254d03d08e2bc9e2d0ab159"></a><!-- doxytag: member="macro68.h::ROXLL" ref="8ea628cee254d03d08e2bc9e2d0ab159" args="(ROR_A, ROR_B)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="macro68_8h.html#8ea628cee254d03d08e2bc9e2d0ab159">ROXLL</a>(ROR_A, ROR_B) ROXL(ROR_A,ROR_B,0xFFFFFFFF,32)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">generic right shift <br></td></tr>
</table>
<hr><h2>Detailed Description</h2>
68K instruction emulation macro definitions.
<p>
<dl class="author" compact><dt><b>Author:</b></dt><dd>Ben(jamin) Gerard <<a href="mailto:ben@sashipa.com">ben@sashipa.com</a>> </dd></dl>
<dl class="date" compact><dt><b>Date:</b></dt><dd>1999/13/03 </dd></dl>
<dl class="version" compact><dt><b>Version:</b></dt><dd></dd></dl>
<dl class="rcs" compact><dt><b>Id</b></dt><dd><a class="el" href="macro68_8h.html" title="68K instruction emulation macro definitions.">macro68.h</a>,v 2.1 2003/09/30 06:29:57 benjihan Exp </dd></dl>
<p>
A important part of EMU68 instruction emulation is done using macro in order to :<ul>
<li>generate decent optimized compiled code.</li><li>simplify compilation process and to avoid "C" code generation. </li></ul>
<hr><h2>Define Documentation</h2>
<a class="anchor" name="20a4f9d1130f259f69dab9c2b32a78e1"></a><!-- doxytag: member="macro68.h::EXCEPTION" ref="20a4f9d1130f259f69dab9c2b32a78e1" args="(VECTOR, LVL)" -->
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<td class="memname">#define EXCEPTION </td>
<td>(</td>
<td class="paramtype">VECTOR, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">LVL </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{ \
<a class="code" href="mem68_8h.html#4eb26386c28cdc607b1fe9e6c60ca863" title="Push long.">pushl</a>(<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#efb01a3243a5348ce52c4aa4fd19fd64" title="68000 Program Counter.">pc</a>); <a class="code" href="mem68_8h.html#dd4547bb78f600d8aec1ca51f87df1b1" title="Push word.">pushw</a>(<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a>); \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0x70FF; \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (0x2000+((LVL)<<<a class="code" href="srdef68_8h.html#f45c0fa5f0bf8aebf64fc0f31b18b72e" title="Internal Processor Level bit number.">SR_IPL_BIT</a>)); \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#efb01a3243a5348ce52c4aa4fd19fd64" title="68000 Program Counter.">pc</a> = <a class="code" href="mem68_8h.html#2b23623a233ab296159535dda8b60b1b" title="Read memory long.">read_L</a>(VECTOR); \
}
</pre></div>General exception or interruption.
<p>
</div>
</div><p>
<a class="anchor" name="50f4496a33308c2325e5c9cea9ccd9f2"></a><!-- doxytag: member="macro68.h::ILLEGAL" ref="50f4496a33308c2325e5c9cea9ccd9f2" args="" -->
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<td class="memname">#define ILLEGAL </td>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="emu68_2error68_8h.html#987a74740a85d2a8ebc3e88fbef0db15" title="Push formatted error message.">EMU68error_add</a>(<span class="stringliteral">"Illegal pc:%06x"</span>,<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#efb01a3243a5348ce52c4aa4fd19fd64" title="68000 Program Counter.">pc</a>); \
<a class="code" href="macro68_8h.html#20a4f9d1130f259f69dab9c2b32a78e1" title="General exception or interruption.">EXCEPTION</a>(<a class="code" href="excep68_8h.html#2c619e75c81653281159f0b99310fa68" title="ILLEGAL vector address.">ILLEGAL_VECTOR</a>,<a class="code" href="excep68_8h.html#c1b9999035e5a5a27842b9ad061e2925" title="ILLEGAL interruption level.">ILLEGAL_LVL</a>); \
}
</pre></div>Illegal instruction.
<p>
</div>
</div><p>
<a class="anchor" name="be98308cc3e5190044294f4f626b4442"></a><!-- doxytag: member="macro68.h::BUSERROR" ref="be98308cc3e5190044294f4f626b4442" args="(ADDR, MODE)" -->
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<td class="memname">#define BUSERROR </td>
<td>(</td>
<td class="paramtype">ADDR, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">MODE </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="emu68_2error68_8h.html#987a74740a85d2a8ebc3e88fbef0db15" title="Push formatted error message.">EMU68error_add</a>(<span class="stringliteral">"bus error pc:%06x addr:%06x (%c)"</span>,\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#efb01a3243a5348ce52c4aa4fd19fd64" title="68000 Program Counter.">pc</a>,ADDR,MODE?<span class="charliteral">'W'</span>:<span class="charliteral">'R'</span>);\
<a class="code" href="macro68_8h.html#20a4f9d1130f259f69dab9c2b32a78e1" title="General exception or interruption.">EXCEPTION</a>(<a class="code" href="excep68_8h.html#4216efa44163ab27805522fb15f8eccd" title="BUSERROR vector address.">BUSERROR_VECTOR</a>,<a class="code" href="excep68_8h.html#71337c31f4cc99de484ab7d795f399d3" title="BUSERROR interruption level.">BUSERROR_LVL</a>) \
}
</pre></div>Bus error exception.
<p>
</div>
</div><p>
<a class="anchor" name="e19b6bb2940d2fbe0a79852b070eeafd"></a><!-- doxytag: member="macro68.h::STOP" ref="e19b6bb2940d2fbe0a79852b070eeafd" args="" -->
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<td class="memname">#define STOP reg68.sr = (<a class="el" href="type68_8h.html#9e6c91d77e24643b888dbd1a1a590054">u16</a>)get_nextw(); reg68.status = 1 </td>
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<p>
STOP.
<p>
<dl class="warning" compact><dt><b>Warning:</b></dt><dd>: Partially hanfdled : only move val;ue to SR </dd></dl>
</div>
</div><p>
<a class="anchor" name="0cbf0b9c373ada722f2e3940a8e837a3"></a><!-- doxytag: member="macro68.h::CLR" ref="0cbf0b9c373ada722f2e3940a8e837a3" args="(CLR_S, CLR_A)" -->
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<td class="memname">#define CLR </td>
<td>(</td>
<td class="paramtype">CLR_S, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">CLR_A </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
(CLR_A) = (CLR_A); \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> =(<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a>&~(<a class="code" href="srdef68_8h.html#4e20b1ac95c6469063cd85ff839c6c01" title="Negative value.">SR_N</a>|<a class="code" href="srdef68_8h.html#e147775240980f758cd0152a625724fe" title="Overflow value.">SR_V</a>|<a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a>)) | <a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>;\
CLR_S = 0;\
}
</pre></div>Generic clear memory or register.
<p>
</div>
</div><p>
<a class="anchor" name="cabdc746fdfa7e8a587104efcd13b145"></a><!-- doxytag: member="macro68.h::LINK" ref="cabdc746fdfa7e8a587104efcd13b145" args="(R_LNK)" -->
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<td class="memname">#define LINK </td>
<td>(</td>
<td class="paramtype">R_LNK </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="mem68_8h.html#4eb26386c28cdc607b1fe9e6c60ca863" title="Push long.">pushl</a>(<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[R_LNK]); \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[R_LNK] = <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[7]; \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[7] += <a class="code" href="mem68_8h.html#491b502d64966b1a2cbf5096eebb35f3" title="Decode word and update PC.">get_nextw</a>()
</pre></div>Link (frame pointer).
<p>
</div>
</div><p>
<a class="anchor" name="207482409eaa458a93dc02f7f89a55fe"></a><!-- doxytag: member="macro68.h::UNLK" ref="207482409eaa458a93dc02f7f89a55fe" args="(R_LNK)" -->
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<td class="memname">#define UNLK </td>
<td>(</td>
<td class="paramtype">R_LNK </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[7]=<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[R_LNK]; \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#30ccf2eb74279ccceb995feb6dbd4321" title="68000 address registers.">a</a>[R_LNK]=<a class="code" href="mem68_8h.html#25d71bd3256a69045302f1d106bac627" title="Pop long.">popl</a>()
</pre></div>UNLK (frame pointer).
<p>
</div>
</div><p>
<a class="anchor" name="437700508dff5a665d62caed6d19962a"></a><!-- doxytag: member="macro68.h::SWAP" ref="437700508dff5a665d62caed6d19962a" args="(SWP_A)" -->
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<td class="memname">#define SWAP </td>
<td>(</td>
<td class="paramtype">SWP_A </td>
<td class="paramname"> </td>
<td> ) </td>
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<b>Value:</b><div class="fragment"><pre class="fragment">{ \
(SWP_A) = ((<a class="code" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049" title="Must be an unsigned 32 bit integer.">u32</a>)(SWP_A)>>16) | ((SWP_A)<<16); \
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> = (<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a>&~(<a class="code" href="srdef68_8h.html#e147775240980f758cd0152a625724fe" title="Overflow value.">SR_V</a>|<a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a>|<a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>|<a class="code" href="srdef68_8h.html#4e20b1ac95c6469063cd85ff839c6c01" title="Negative value.">SR_N</a>)) | \
((!(SWP_A))<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | \
(((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(SWP_A)>>31)&<a class="code" href="srdef68_8h.html#4e20b1ac95c6469063cd85ff839c6c01" title="Negative value.">SR_N</a>); \
}
</pre></div>Register value swapping.
<p>
</div>
</div><p>
<a class="anchor" name="9e3dfa1ebebfd77f10b81218e221b141"></a><!-- doxytag: member="macro68.h::BSET" ref="9e3dfa1ebebfd77f10b81218e221b141" args="(V, BIT)" -->
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<td class="memname">#define BSET </td>
<td>(</td>
<td class="paramtype">V, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">BIT </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
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</div>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">if</span>( (V)&(1<<(BIT)) ) { <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= ~<a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>; }\
<span class="keywordflow">else</span> { (V) |= 1<<(BIT); <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>; }
</pre></div>Bit set.
<p>
</div>
</div><p>
<a class="anchor" name="9c1e975d7c0e874a2110b6bb1c26fe1a"></a><!-- doxytag: member="macro68.h::BCLR" ref="9c1e975d7c0e874a2110b6bb1c26fe1a" args="(V, BIT)" -->
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<td class="memname">#define BCLR </td>
<td>(</td>
<td class="paramtype">V, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">BIT </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">if</span>( (V)&(1<<(BIT)) ) { (V) &= ~(1<<(BIT)); <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= ~<a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>; }\
<span class="keywordflow">else</span> { <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>; }
</pre></div>Bit clear.
<p>
</div>
</div><p>
<a class="anchor" name="09f70aac938aa9c8b83269d32d347121"></a><!-- doxytag: member="macro68.h::BCHG" ref="09f70aac938aa9c8b83269d32d347121" args="(V, BIT)" -->
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<td class="memname">#define BCHG </td>
<td>(</td>
<td class="paramtype">V, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">BIT </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">if</span>( (V)&(1<<(BIT)) ) { (V) &= ~(1<<(BIT)); <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= ~<a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>; }\
<span class="keywordflow">else</span> { (V) |= 1<<(BIT); <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#7847483f951ee91343d93a74fffb13dd" title="Zero value.">SR_Z</a>; }
</pre></div>Bit change.
<p>
</div>
</div><p>
<a class="anchor" name="dc0f71c5fe123b5bb3123ff29adbf8c9"></a><!-- doxytag: member="macro68.h::MOVE" ref="dc0f71c5fe123b5bb3123ff29adbf8c9" args="(MOV_A)" -->
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<td class="memname">#define MOVE </td>
<td>(</td>
<td class="paramtype">MOV_A </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
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</div>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> = (<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a>&(0xFF00 | <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a>)) \
| (((MOV_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(MOV_A)>>31)&<a class="code" href="srdef68_8h.html#4e20b1ac95c6469063cd85ff839c6c01" title="Negative value.">SR_N</a>);
</pre></div>
</div>
</div><p>
<a class="anchor" name="79a596a6a422c8d33ede561cf1fe5666"></a><!-- doxytag: member="macro68.h::SUBAW" ref="79a596a6a422c8d33ede561cf1fe5666" args="(SUB_S, SUB_A, SUB_B)" -->
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<td class="memname">#define SUBAW </td>
<td>(</td>
<td class="paramtype">SUB_S, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">SUB_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">SUB_B </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a> ZOB = (SUB_A)>>16;\
SUBA(SUB_S, ZOB, SUB_B);\
}
</pre></div>
</div>
</div><p>
<a class="anchor" name="e13bda8d99705b03baf6a1b8b6036839"></a><!-- doxytag: member="macro68.h::CMPAW" ref="e13bda8d99705b03baf6a1b8b6036839" args="(CMP_A, CMP_B)" -->
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<td class="memname">#define CMPAW </td>
<td>(</td>
<td class="paramtype">CMP_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">CMP_B </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a> ZOB = (CMP_A)>>16;\
CMPA( ZOB, CMP_B);\
}
</pre></div>
</div>
</div><p>
<a class="anchor" name="62f78dccd3f300863730f230b762b17b"></a><!-- doxytag: member="macro68.h::LSR" ref="62f78dccd3f300863730f230b762b17b" args="(LSR_A, LSR_D, LSR_MSK, LSR_C)" -->
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<td class="memname">#define LSR </td>
<td>(</td>
<td class="paramtype">LSR_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">LSR_D, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">LSR_MSK, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">LSR_C </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0xFF00;\
<span class="keywordflow">if</span>((LSR_D)!=0) \
{\
<a class="code" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b" title="Dummy internal cycle counter.">ADDCYCLE</a>(2*(LSR_D));\
(LSR_A) >>= (LSR_D)-1;\
<span class="keywordflow">if</span>((LSR_A)&(LSR_C)) <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a> | <a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a>;\
(LSR_A)>>=1;\
}\
(LSR_A) &= (LSR_MSK);\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (((LSR_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(LSR_A)<0)<<<a class="code" href="srdef68_8h.html#5af5c659d4673612805983337d980478" title="Negative bit number.">SR_N_BIT</a>);\
}
</pre></div>generic right shift
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</div>
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<a class="anchor" name="32f934a87ef94acfd506fba08a9df435"></a><!-- doxytag: member="macro68.h::LSL" ref="32f934a87ef94acfd506fba08a9df435" args="(LSL_A, LSL_D, LSL_MSK)" -->
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<td class="memname">#define LSL </td>
<td>(</td>
<td class="paramtype">LSL_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">LSL_D, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">LSL_MSK </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
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<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0xFF00;\
<span class="keywordflow">if</span>((LSL_D)!=0) \
{\
<a class="code" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b" title="Dummy internal cycle counter.">ADDCYCLE</a>(2*(LSL_D));\
(LSL_A) <<= (LSL_D)-1;\
<span class="keywordflow">if</span>((LSL_A)&0x80000000) <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a> | <a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a>;\
(LSL_A)<<=1;\
}\
(LSL_A) &= (LSL_MSK);\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (((LSL_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(LSL_A)<0)<<<a class="code" href="srdef68_8h.html#5af5c659d4673612805983337d980478" title="Negative bit number.">SR_N_BIT</a>);\
}
</pre></div>Generic left shift.
<p>
</div>
</div><p>
<a class="anchor" name="b68fd08adcd92db17b1105faedc53039"></a><!-- doxytag: member="macro68.h::ROR" ref="b68fd08adcd92db17b1105faedc53039" args="(ROR_A, ROR_D, ROR_MSK, ROR_SZ)" -->
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<td class="memname">#define ROR </td>
<td>(</td>
<td class="paramtype">ROR_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_D, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_MSK, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_SZ </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0xFF00 | <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a>;\
<span class="keywordflow">if</span>((ROR_D)!=0) \
{\
<a class="code" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b" title="Dummy internal cycle counter.">ADDCYCLE</a>(2*(ROR_D));\
ROR_D &= (ROR_SZ)-1;\
<span class="keywordflow">if</span>((ROR_A)&(1<<((ROR_D)-1+32-(ROR_SZ)))) <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a>;\
(ROR_A) &= (ROR_MSK);\
(ROR_A) = ((ROR_A)>>(ROR_D)) + ((ROR_A)<<((ROR_SZ)-(ROR_D)));\
}\
(ROR_A) &= (ROR_MSK);\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (((ROR_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(ROR_A)<0)<<<a class="code" href="srdef68_8h.html#5af5c659d4673612805983337d980478" title="Negative bit number.">SR_N_BIT</a>);\
}
</pre></div>Generic right rotation.
<p>
</div>
</div><p>
<a class="anchor" name="9256b88e92d07a399381ca524df5ee31"></a><!-- doxytag: member="macro68.h::ROL" ref="9256b88e92d07a399381ca524df5ee31" args="(ROR_A, ROR_D, ROR_MSK, ROR_SZ)" -->
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<td class="memname">#define ROL </td>
<td>(</td>
<td class="paramtype">ROR_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_D, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_MSK, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_SZ </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0xFF00 | <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a>;\
<span class="keywordflow">if</span>((ROR_D)!=0) \
{\
<a class="code" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b" title="Dummy internal cycle counter.">ADDCYCLE</a>(2*(ROR_D));\
ROR_D &= (ROR_SZ)-1;\
<span class="keywordflow">if</span>((ROR_A)&(1<<(32-(ROR_D)))) <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a>;\
(ROR_A) &= (ROR_MSK);\
(ROR_A) = ((ROR_A)<<(ROR_D)) + ((ROR_A)>>((ROR_SZ)-(ROR_D)));\
}\
(ROR_A) &= (ROR_MSK);\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (((ROR_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(ROR_A)<0)<<<a class="code" href="srdef68_8h.html#5af5c659d4673612805983337d980478" title="Negative bit number.">SR_N_BIT</a>);\
}
</pre></div>Generic left rotation.
<p>
</div>
</div><p>
<a class="anchor" name="c345ba876fb038f47a015001da1552f5"></a><!-- doxytag: member="macro68.h::ROXR" ref="c345ba876fb038f47a015001da1552f5" args="(ROR_A, ROR_D, ROR_MSK, ROR_SZ)" -->
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<td class="memname">#define ROXR </td>
<td>(</td>
<td class="paramtype">ROR_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_D, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_MSK, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_SZ </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049" title="Must be an unsigned 32 bit integer.">u32</a> ROR_X = (<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a>>><a class="code" href="srdef68_8h.html#1bdabe3e9a0a2adffdce5ab1b48c8e30" title="eXtended carry bit number">SR_X_BIT</a>)&1;\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0xFF00;\
<span class="keywordflow">if</span>((ROR_D)!=0) \
{\
<a class="code" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b" title="Dummy internal cycle counter.">ADDCYCLE</a>(2*(ROR_D));\
ROR_D &= (ROR_SZ)-1;\
<span class="keywordflow">if</span>((ROR_A)&(1<<((ROR_D)-1+32-(ROR_SZ)))) <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a> | <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a>;\
(ROR_A) &= (ROR_MSK);\
(ROR_A) = ((ROR_A)>>(ROR_D)) + ((ROR_A)<<((ROR_SZ)-(ROR_D)+1));\
(ROR_A) |= (ROR_X)<<(32-(ROR_D));\
}\
(ROR_A) &= (ROR_MSK);\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (((ROR_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(ROR_A)<0)<<<a class="code" href="srdef68_8h.html#5af5c659d4673612805983337d980478" title="Negative bit number.">SR_N_BIT</a>);\
}
</pre></div>Generic right extend-bit rotation.
<p>
</div>
</div><p>
<a class="anchor" name="fc5f222e265883f0ef3153798efa2cce"></a><!-- doxytag: member="macro68.h::ROXL" ref="fc5f222e265883f0ef3153798efa2cce" args="(ROR_A, ROR_D, ROR_MSK, ROR_SZ)" -->
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<td class="memname">#define ROXL </td>
<td>(</td>
<td class="paramtype">ROR_A, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_D, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_MSK, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">ROR_SZ </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">{\
<a class="code" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049" title="Must be an unsigned 32 bit integer.">u32</a> ROR_X = (<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a>>><a class="code" href="srdef68_8h.html#1bdabe3e9a0a2adffdce5ab1b48c8e30" title="eXtended carry bit number">SR_X_BIT</a>)&1;\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> &= 0xFF00;\
<span class="keywordflow">if</span>((ROR_D)!=0) \
{\
<a class="code" href="macro68_8h.html#6854f97787c2c6fc81de10084518e83b" title="Dummy internal cycle counter.">ADDCYCLE</a>(2*(ROR_D));\
ROR_D &= (ROR_SZ)-1;\
<span class="keywordflow">if</span>((ROR_A)&(1<<(32-(ROR_D)))) <a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= <a class="code" href="srdef68_8h.html#ab737dff2860e37fbd9e08c30eaa0364" title="Carry value.">SR_C</a> | <a class="code" href="srdef68_8h.html#2037ff64b19633dfd3b54da9d05784d9" title="eXtended carry value">SR_X</a> ;\
(ROR_A) &= (ROR_MSK);\
(ROR_A) = ((ROR_A)<<(ROR_D)) + ((ROR_A)>>((ROR_SZ)-(ROR_D)+1));\
(ROR_A) |= (ROR_X)<<((ROR_D)-1+(32-(ROR_SZ)));\
}\
(ROR_A) &= (ROR_MSK);\
<a class="code" href="emu68_8h.html#f7cf07d04cacbed7604dbf6b432bed3c" title="EMU68 internal 68K register set structure.">reg68</a>.<a class="code" href="structreg68__t.html#b1fe12b1ee7fa5e52077801c5618f20d" title="68000 Status Register.">sr</a> |= (((ROR_A)==0)<<<a class="code" href="srdef68_8h.html#61358487950b723851177611ac385abf" title="Zero bit number.">SR_Z_BIT</a>) | (((<a class="code" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6" title="Must be an signed 32 bit integer.">s32</a>)(ROR_A)<0)<<<a class="code" href="srdef68_8h.html#5af5c659d4673612805983337d980478" title="Negative bit number.">SR_N_BIT</a>);\
}
</pre></div>Generic left extend-bit rotation.
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