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<h1>/home/mandrake/rpm/BUILD/sc68-2.2.1/emu68/mem68.h File Reference</h1>68k memory and IO manager.
<a href="#_details">More...</a>
<p>
<code>#include "<a class="el" href="struct68_8h_source.html">emu68/struct68.h</a>"</code><br>
<p>
<a href="mem68_8h_source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Memory access flags for reg68.chk (debug mode only).</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0b190105733e27383c81d3e3f3b52dff"></a><!-- doxytag: member="mem68.h::READ_68" ref="0b190105733e27383c81d3e3f3b52dff" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#0b190105733e27383c81d3e3f3b52dff">READ_68</a> 1</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Memory location has been read. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bde7e7f895b3a64f4e51675880687b3b"></a><!-- doxytag: member="mem68.h::WRITTEN_68" ref="bde7e7f895b3a64f4e51675880687b3b" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#bde7e7f895b3a64f4e51675880687b3b">WRITTEN_68</a> 2</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Memory location has been written. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c5a6be57d418e972cdfc92e468f2948b"></a><!-- doxytag: member="mem68.h::EXECUTED_68" ref="c5a6be57d418e972cdfc92e468f2948b" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#c5a6be57d418e972cdfc92e468f2948b">EXECUTED_68</a> 4</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Memory location has been executed. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="71ce35bedc7e3ef87192a5553a3b5970"></a><!-- doxytag: member="mem68.h::BREAKED_68" ref="71ce35bedc7e3ef87192a5553a3b5970" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#71ce35bedc7e3ef87192a5553a3b5970">BREAKED_68</a> 8</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Memory location has emulator-breakpoint. <br></td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#7ab1612114640865978f1d94411443c1">EMU68memory_init</a> (void)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Init memory quick access table. <a href="#7ab1612114640865978f1d94411443c1"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#66bee84e7104d02dad201c9790f87d3f">EMU68memory_reset</a> (void)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Reset memory quick access table. <a href="#66bee84e7104d02dad201c9790f87d3f"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#e3042993b857d7ccc087cbab14ee2199">EMU68memory_new_area</a> (<a class="el" href="type68_8h.html#ed742c436da53c1080638ce6ef7d13de">u8</a> area, <a class="el" href="struct68_8h.html#64f9293b17caaf5b9c65f60847cbf2f7">memrfunc68_t</a> *read_bwl, <a class="el" href="struct68_8h.html#a7f3d5219ebba18afaf36412f39f67ba">memwfunc68_t</a> *write_bwl)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Add a new memory access control area (for new IO). <a href="#e3042993b857d7ccc087cbab14ee2199"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#288deb0e97edc1ac9fbec446e3665353">EMU68memory_reset_area</a> (<a class="el" href="type68_8h.html#ed742c436da53c1080638ce6ef7d13de">u8</a> area)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Reset memory access control area to default state. <a href="#288deb0e97edc1ac9fbec446e3665353"></a><br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Instruction read.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="491b502d64966b1a2cbf5096eebb35f3"></a><!-- doxytag: member="mem68.h::get_nextw" ref="491b502d64966b1a2cbf5096eebb35f3" args="(void)" -->
<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#491b502d64966b1a2cbf5096eebb35f3">get_nextw</a> (void)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Decode word and update PC. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ff32f9f1177449f4f6caad61495cf8a2"></a><!-- doxytag: member="mem68.h::get_nextl" ref="ff32f9f1177449f4f6caad61495cf8a2" args="(void)" -->
<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#ff32f9f1177449f4f6caad61495cf8a2">get_nextl</a> (void)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Decode long and update PC. <br></td></tr>
<tr><td colspan="2"><div class="groupHeader">Stack access.</div></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4eb26386c28cdc607b1fe9e6c60ca863"></a><!-- doxytag: member="mem68.h::pushl" ref="4eb26386c28cdc607b1fe9e6c60ca863" args="(s32 v)" -->
void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#4eb26386c28cdc607b1fe9e6c60ca863">pushl</a> (<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a> v)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Push long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dd4547bb78f600d8aec1ca51f87df1b1"></a><!-- doxytag: member="mem68.h::pushw" ref="dd4547bb78f600d8aec1ca51f87df1b1" args="(s32 v)" -->
void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#dd4547bb78f600d8aec1ca51f87df1b1">pushw</a> (<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a> v)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Push word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="25d71bd3256a69045302f1d106bac627"></a><!-- doxytag: member="mem68.h::popl" ref="25d71bd3256a69045302f1d106bac627" args="(void)" -->
<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#25d71bd3256a69045302f1d106bac627">popl</a> (void)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Pop long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c5d328e5d7b2321f5f18ec0bc5ab0290"></a><!-- doxytag: member="mem68.h::popw" ref="c5d328e5d7b2321f5f18ec0bc5ab0290" args="(void)" -->
<a class="el" href="type68_8h.html#0ce6887c26c1c49ad3be5710dd42bfd6">s32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#c5d328e5d7b2321f5f18ec0bc5ab0290">popw</a> (void)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Pop word. <br></td></tr>
<tr><td colspan="2"><br><h2>Memory/IO quick access tables.</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b1232283b5d7360c24b551a89c8a34ca"></a><!-- doxytag: member="mem68.h::ISIO68" ref="b1232283b5d7360c24b551a89c8a34ca" args="(ADDR)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#b1232283b5d7360c24b551a89c8a34ca">ISIO68</a>(ADDR) ((ADDR)&0x800000)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Test for direct memory access or IO quick table access. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3162f2f610fdb76ee541c3d6bfc506f1"></a><!-- doxytag: member="mem68.h::read_mem_jmp_l" ref="3162f2f610fdb76ee541c3d6bfc506f1" args="[256]" -->
<a class="el" href="struct68_8h.html#64f9293b17caaf5b9c65f60847cbf2f7">memrfunc68_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#3162f2f610fdb76ee541c3d6bfc506f1">read_mem_jmp_l</a> [256]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="68b16946b38460b3fe776898ad117ad6"></a><!-- doxytag: member="mem68.h::read_mem_jmp_w" ref="68b16946b38460b3fe776898ad117ad6" args="[256]" -->
<a class="el" href="struct68_8h.html#64f9293b17caaf5b9c65f60847cbf2f7">memrfunc68_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#68b16946b38460b3fe776898ad117ad6">read_mem_jmp_w</a> [256]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="124df94027b2f4ccf7c084a140db6d0b"></a><!-- doxytag: member="mem68.h::read_mem_jmp_b" ref="124df94027b2f4ccf7c084a140db6d0b" args="[256]" -->
<a class="el" href="struct68_8h.html#64f9293b17caaf5b9c65f60847cbf2f7">memrfunc68_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#124df94027b2f4ccf7c084a140db6d0b">read_mem_jmp_b</a> [256]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read byte. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6a47da27b0c76089529941a0ddd100d6"></a><!-- doxytag: member="mem68.h::write_mem_jmp_l" ref="6a47da27b0c76089529941a0ddd100d6" args="[256]" -->
<a class="el" href="struct68_8h.html#a7f3d5219ebba18afaf36412f39f67ba">memwfunc68_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#6a47da27b0c76089529941a0ddd100d6">write_mem_jmp_l</a> [256]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e6d3075016d2f6cb4d8847791a320061"></a><!-- doxytag: member="mem68.h::write_mem_jmp_w" ref="e6d3075016d2f6cb4d8847791a320061" args="[256]" -->
<a class="el" href="struct68_8h.html#a7f3d5219ebba18afaf36412f39f67ba">memwfunc68_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#e6d3075016d2f6cb4d8847791a320061">write_mem_jmp_w</a> [256]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="eb5aae9ce258c96f9353b809b0ac16cb"></a><!-- doxytag: member="mem68.h::write_mem_jmp_b" ref="eb5aae9ce258c96f9353b809b0ac16cb" args="[256]" -->
<a class="el" href="struct68_8h.html#a7f3d5219ebba18afaf36412f39f67ba">memwfunc68_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#eb5aae9ce258c96f9353b809b0ac16cb">write_mem_jmp_b</a> [256]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write byte. <br></td></tr>
<tr><td colspan="2"><br><h2>68K onboard memory access.</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f1a5a422081c99f46647c5f2c0aa12e9"></a><!-- doxytag: member="mem68.h::read_B" ref="f1a5a422081c99f46647c5f2c0aa12e9" args="(ADDR)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#f1a5a422081c99f46647c5f2c0aa12e9">read_B</a>(ADDR) read_68000mem_b(ADDR)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read memory byte. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="67c9371c6cab2f4f2a1c6f88de6c5237"></a><!-- doxytag: member="mem68.h::read_W" ref="67c9371c6cab2f4f2a1c6f88de6c5237" args="(ADDR)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#67c9371c6cab2f4f2a1c6f88de6c5237">read_W</a>(ADDR) read_68000mem_w(ADDR)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read memory word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2b23623a233ab296159535dda8b60b1b"></a><!-- doxytag: member="mem68.h::read_L" ref="2b23623a233ab296159535dda8b60b1b" args="(ADDR)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#2b23623a233ab296159535dda8b60b1b">read_L</a>(ADDR) read_68000mem_l(ADDR)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read memory long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb23ed179c2bb5953900eea074f536af"></a><!-- doxytag: member="mem68.h::write_B" ref="bb23ed179c2bb5953900eea074f536af" args="(ADDR, VAL)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#bb23ed179c2bb5953900eea074f536af">write_B</a>(ADDR, VAL) write_68000mem_b(ADDR,VAL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write memory byte. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0f8db1035c761930c11dc35972f86ed4"></a><!-- doxytag: member="mem68.h::write_W" ref="0f8db1035c761930c11dc35972f86ed4" args="(ADDR, VAL)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#0f8db1035c761930c11dc35972f86ed4">write_W</a>(ADDR, VAL) write_68000mem_w(ADDR,VAL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write memory word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1e727f68c5a2175c39f221473ea62970"></a><!-- doxytag: member="mem68.h::write_L" ref="1e727f68c5a2175c39f221473ea62970" args="(ADDR, VAL)" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#1e727f68c5a2175c39f221473ea62970">write_L</a>(ADDR, VAL) write_68000mem_l(ADDR,VAL)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write memory long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5f7cd35afc0cff72c173e6b222f44b16"></a><!-- doxytag: member="mem68.h::read_68000mem_b" ref="5f7cd35afc0cff72c173e6b222f44b16" args="(u32 addr)" -->
<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#5f7cd35afc0cff72c173e6b222f44b16">read_68000mem_b</a> (<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> addr)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read memory byte. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="48e7b6a1881904c1b6df5997e9847471"></a><!-- doxytag: member="mem68.h::read_68000mem_w" ref="48e7b6a1881904c1b6df5997e9847471" args="(u32 addr)" -->
<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#48e7b6a1881904c1b6df5997e9847471">read_68000mem_w</a> (<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> addr)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read memory word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8c8540d1a927827882d06c5ece78830f"></a><!-- doxytag: member="mem68.h::read_68000mem_l" ref="8c8540d1a927827882d06c5ece78830f" args="(u32 addr)" -->
<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#8c8540d1a927827882d06c5ece78830f">read_68000mem_l</a> (<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> addr)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read memory long. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1f3677ccc89d8cf0e2f6d01545a21890"></a><!-- doxytag: member="mem68.h::write_68000mem_b" ref="1f3677ccc89d8cf0e2f6d01545a21890" args="(u32 addr, u32 v)" -->
void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#1f3677ccc89d8cf0e2f6d01545a21890">write_68000mem_b</a> (<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> addr, <a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> v)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write memory byte. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="303bd23beedc50bee2e13509eaa3a710"></a><!-- doxytag: member="mem68.h::write_68000mem_w" ref="303bd23beedc50bee2e13509eaa3a710" args="(u32 addr, u32 v)" -->
void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#303bd23beedc50bee2e13509eaa3a710">write_68000mem_w</a> (<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> addr, <a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> v)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write memory word. <br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ab7037371b7355a2513d733ab3c1f6b5"></a><!-- doxytag: member="mem68.h::write_68000mem_l" ref="ab7037371b7355a2513d733ab3c1f6b5" args="(u32 addr, u32 v)" -->
void </td><td class="memItemRight" valign="bottom"><a class="el" href="mem68_8h.html#ab7037371b7355a2513d733ab3c1f6b5">write_68000mem_l</a> (<a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> addr, <a class="el" href="type68_8h.html#10e94b422ef0c20dcdec20d31a1f5049">u32</a> v)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write memory long. <br></td></tr>
</table>
<hr><h2>Detailed Description</h2>
68k memory and IO manager.
<p>
<dl class="author" compact><dt><b>Author:</b></dt><dd>Benjamin Gerard <<a href="mailto:ben@sashipa.com">ben@sashipa.com</a>> </dd></dl>
<dl class="date" compact><dt><b>Date:</b></dt><dd>13/03/1999 </dd></dl>
<dl class="version" compact><dt><b>Version:</b></dt><dd></dd></dl>
<dl class="rcs" compact><dt><b>Id</b></dt><dd><a class="el" href="mem68_8h.html" title="68k memory and IO manager.">mem68.h</a>,v 2.1 2003/09/30 06:29:57 benjihan Exp </dd></dl>
<p>
EMU68 memory manager assumes that all addresses in the lowest half part of address space are memory access. A simple bit test over most signifiant bit (23) of address allow to choose beetween memory or eventual IO access. In case of memory access, address is masked to fit available 68K onboard memory. Overflow does NOT generate address error. IO access are performed towards quick access tables. There are 6 acccess tables: for each read and write access in 3 sizes (byte, word and long). Each of this 6 tables has 256 entries filled with a pointer to suitable function. At init time, the entries of all tables are initialized to access 68K onboard memory. When an IO is plugged by user, it is mapped somewhere in 68K address space. EMU68 memory manager get bit 8 to 15 of address to make an index to be used in the suitable table (R/W for B/W/L).<p>
Featuring<ul>
<li>Onboard memory byte, word and long read/write access.</li><li>Optimized IO warm mapping/unmapping.</li><li>Optionnal (compile time) enhanced memory control with RWX access tag and hardware breakpoints.</li></ul>
<p>
Limitations<ul>
<li>For optimization purposes IO must be mapped in high half memory (bit 23 of address setted).</li><li>Two IO can not shared the same memory location for bit 8 to 15. Conflicts could be resolved by creating an intermediate IO which dispatches to others. This mechanism has not been implemented yet, so users must do it them self if needed.</li></ul>
<p>
Atari-ST & Amiga IO areas<ul>
<li><code>FF8800-FF88FF</code> : YM2149 (ST)</li><li><code>FF8900-FF89FF</code> : Micro-Wire (STE)</li><li><code>FF8200-FF82FF</code> : Shifter (ST)</li><li><code>FFFA00-FFFAFF</code> : MFP (ST)</li><li><code>DFF000-DFF0DF</code> : Paula (AMIGA) </li></ul>
<hr><h2>Function Documentation</h2>
<a class="anchor" name="7ab1612114640865978f1d94411443c1"></a><!-- doxytag: member="mem68.h::EMU68memory_init" ref="7ab1612114640865978f1d94411443c1" args="(void)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">void EMU68memory_init </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
Init memory quick access table.
<p>
The <a class="el" href="mem68_8h.html#7ab1612114640865978f1d94411443c1" title="Init memory quick access table.">EMU68memory_init()</a> function must be call at init time. Currently this function only call the <a class="el" href="mem68_8h.html#66bee84e7104d02dad201c9790f87d3f" title="Reset memory quick access table.">EMU68memory_reset()</a> function.<p>
<dl class="see" compact><dt><b>See also:</b></dt><dd><a class="el" href="mem68_8h.html#66bee84e7104d02dad201c9790f87d3f" title="Reset memory quick access table.">EMU68memory_reset()</a> </dd></dl>
</div>
</div><p>
<a class="anchor" name="66bee84e7104d02dad201c9790f87d3f"></a><!-- doxytag: member="mem68.h::EMU68memory_reset" ref="66bee84e7104d02dad201c9790f87d3f" args="(void)" -->
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<div class="memproto">
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<td class="memname">void EMU68memory_reset </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
Reset memory quick access table.
<p>
The <a class="el" href="mem68_8h.html#66bee84e7104d02dad201c9790f87d3f" title="Reset memory quick access table.">EMU68memory_reset()</a> function restores all memory access to default. All mapped IO will be discard and replace by onboard memory access.
</div>
</div><p>
<a class="anchor" name="e3042993b857d7ccc087cbab14ee2199"></a><!-- doxytag: member="mem68.h::EMU68memory_new_area" ref="e3042993b857d7ccc087cbab14ee2199" args="(u8 area, memrfunc68_t *read_bwl, memwfunc68_t *write_bwl)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">void EMU68memory_new_area </td>
<td>(</td>
<td class="paramtype"><a class="el" href="type68_8h.html#ed742c436da53c1080638ce6ef7d13de">u8</a> </td>
<td class="paramname"> <em>area</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="struct68_8h.html#64f9293b17caaf5b9c65f60847cbf2f7">memrfunc68_t</a> * </td>
<td class="paramname"> <em>read_bwl</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="struct68_8h.html#a7f3d5219ebba18afaf36412f39f67ba">memwfunc68_t</a> * </td>
<td class="paramname"> <em>write_bwl</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
Add a new memory access control area (for new IO).
<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>area</em> </td><td>Which area (bit 16 to 23 of address) to change. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>read_bwl</em> </td><td>Read function table (byte, word and long in this order) </td></tr>
<tr><td valign="top"></td><td valign="top"><em>write_bwl</em> </td><td>idem read_bwl for write access.</td></tr>
</table>
</dl>
<dl class="see" compact><dt><b>See also:</b></dt><dd><a class="el" href="mem68_8h.html#288deb0e97edc1ac9fbec446e3665353" title="Reset memory access control area to default state.">EMU68memory_reset_area()</a> </dd></dl>
</div>
</div><p>
<a class="anchor" name="288deb0e97edc1ac9fbec446e3665353"></a><!-- doxytag: member="mem68.h::EMU68memory_reset_area" ref="288deb0e97edc1ac9fbec446e3665353" args="(u8 area)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void EMU68memory_reset_area </td>
<td>(</td>
<td class="paramtype"><a class="el" href="type68_8h.html#ed742c436da53c1080638ce6ef7d13de">u8</a> </td>
<td class="paramname"> <em>area</em> </td>
<td> ) </td>
<td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
Reset memory access control area to default state.
<p>
<dl class="see" compact><dt><b>See also:</b></dt><dd><a class="el" href="mem68_8h.html#e3042993b857d7ccc087cbab14ee2199" title="Add a new memory access control area (for new IO).">EMU68memory_new_area()</a> </dd></dl>
</div>
</div><p>
</div>
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