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<H2><A NAME="SECTION00070000000000000000">
Bibliography</A>
</H2><DL COMPACT><DD><P></P><DT><A NAME="Bahar93">1</A>
<DD>
R.&nbsp;I. Bahar, E.&nbsp;A. Frohm, C.&nbsp;M. Gaona, G.&nbsp;D. Hachtel, E.&nbsp;Macii, A.&nbsp;Pardo, and
  F.&nbsp;Somenzi.
<BR>Algebraic decision diagrams and their applications.
<BR>In <EM>Proceedings of the International Conference on Computer-Aided
  Design</EM>, pages 188-191, Santa Clara, CA, November 1993.

<P></P><DT><A NAME="Bollig95">2</A>
<DD>
B.&nbsp;Bollig, M.&nbsp;L&#246;bbing, and I.&nbsp;Wegener.
<BR>Simulated annealing to improve variable orderings for OBDDs.
<BR>Presented at the International Workshop on Logic Synthesis,
  Granlibakken, CA, May 1995.

<P></P><DT><A NAME="BBR">3</A>
<DD>
K.&nbsp;S. Brace, R.&nbsp;L. Rudell, and R.&nbsp;E. Bryant.
<BR>Efficient implementation of a BDD package.
<BR>In <EM>Proceedings of the 27th Design Automation Conference</EM>, pages
  40-45, Orlando, FL, June 1990.

<P></P><DT><A NAME="VIS">4</A>
<DD>
R.&nbsp;K. Brayton et&nbsp;al.
<BR>VIS: A system for verification and synthesis.
<BR>Technical Report UCB/ERL M95/104, Electronics Research Lab, Univ. of
  California, December 1995.

<P></P><DT><A NAME="BDD">5</A>
<DD>
R.&nbsp;E. Bryant.
<BR>Graph-based algorithms for Boolean function manipulation.
<BR><EM>IEEE Transactions on Computers</EM>, C-35(8):677-691, August 1986.

<P></P><DT><A NAME="Drechs95">6</A>
<DD>
R.&nbsp;Drechsler, B.&nbsp;Becker, and N.&nbsp;G&#246;ckel.
<BR>A genetic algorithm for variable ordering of OBDDs.
<BR>Presented at the International Workshop on Logic Synthesis,
  Granlibakken, CA, May 1995.

<P></P><DT><A NAME="Friedman90">7</A>
<DD>
S.&nbsp;J. Friedman and K.&nbsp;J. Supowit.
<BR>Finding the optimal variable ordering for binary decision diagrams.
<BR><EM>IEEE Transactions on Computers</EM>, 39(5):710-713, May 1990.

<P></P><DT><A NAME="Fujita91b">8</A>
<DD>
M.&nbsp;Fujita, Y.&nbsp;Matsunaga, and T.&nbsp;Kakuda.
<BR>On variable ordering of binary decision diagrams for the application
  of multi-level logic synthesis.
<BR>In <EM>Proceedings of the European Conference on Design Automation</EM>,
  pages 50-54, Amsterdam, February 1991.

<P></P><DT><A NAME="Held62">9</A>
<DD>
M.&nbsp;Held and R.&nbsp;M. Karp.
<BR>A dynamic programming approach to sequencing problems.
<BR><EM>J. SIAM</EM>, 10(1):196-210, 1962.

<P></P><DT><A NAME="Ishiur91">10</A>
<DD>
N.&nbsp;Ishiura, H.&nbsp;Sawada, and S.&nbsp;Yajima.
<BR>Minimization of binary decision diagrams based on exchanges of
  variables.
<BR>In <EM>Proceedings of the International Conference on Computer-Aided
  Design</EM>, pages 472-475, Santa Clara, CA, November 1991.

<P></P><DT><A NAME="Jeong93">11</A>
<DD>
S.-W. Jeong, T.-S. Kim, and F.&nbsp;Somenzi.
<BR>An efficient method for optimal BDD ordering computation.
<BR>In <EM>International Conference on VLSI and CAD (ICVC'93)</EM>, Taejon,
  Korea, November 1993.

<P></P><DT><A NAME="Minato93">12</A>
<DD>
S.-I. Minato.
<BR>Zero-suppressed BDDs for set manipulation in combinatorial
  problems.
<BR>In <EM>Proceedings of the Design Automation Conference</EM>, pages
  272-277, Dallas, TX, June 1993.

<P></P><DT><A NAME="Panda95b">13</A>
<DD>
S.&nbsp;Panda and F.&nbsp;Somenzi.
<BR>Who are the variables in your neighborhood.
<BR>In <EM>Proceedings of the International Conference on Computer-Aided
  Design</EM>, pages 74-77, San Jose, CA, November 1995.

<P></P><DT><A NAME="Panda94">14</A>
<DD>
S.&nbsp;Panda, F.&nbsp;Somenzi, and B.&nbsp;F. Plessier.
<BR>Symmetry detection and dynamic variable ordering of decision
  diagrams.
<BR>In <EM>Proceedings of the International Conference on Computer-Aided
  Design</EM>, pages 628-631, San Jose, CA, November 1994.

<P></P><DT><A NAME="Plessi93">15</A>
<DD>
B.&nbsp;F. Plessier.
<BR><EM>A General Framework for Verification of Sequential Circuits</EM>.
<BR>PhD thesis, University of Colorado at Boulder, Dept. of Electrical
  and Computer Engineering, 1993.

<P></P><DT><A NAME="Rudell93">16</A>
<DD>
R.&nbsp;Rudell.
<BR>Dynamic variable ordering for ordered binary decision diagrams.
<BR>In <EM>Proceedings of the International Conference on Computer-Aided
  Design</EM>, pages 42-47, Santa Clara, CA, November 1993.

<P></P><DT><A NAME="Sentov92">17</A>
<DD>
E.&nbsp;M. Sentovich, K.&nbsp;J. Singh, C.&nbsp;Moon, H.&nbsp;Savoj, R.&nbsp;K. Brayton, and
  A.&nbsp;Sangiovanni-Vincentelli.
<BR>Sequential circuit design using synthesis and optimization.
<BR>In <EM>Proceedings of the International Conference on Computer
  Design</EM>, pages 328-333, Cambridge, MA, October 1992.
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<P>
<BR><HR>
<ADDRESS>
Fabio Somenzi
2005-05-17
</ADDRESS>
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